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PRELIMINARY INFORMATION
MK2732-06 Low Phase Noise VCXO+Multiplier
Features
* Packaged in 16 pin TSSOP * For xDSL chipsets * For MPEG 2 decoders * Replaces a VCXO and multiplier * Uses an inexpensive pullable crystal * On-chip patented VCXO with pull range of 200 ppm (100 ppm) minimum * VCXO tuning voltage of 0 to 3 V * Zero ppm synthesis error in all clocks * Full CMOS output swings with 25 mA output drive capability at TTL levels * Advanced, low power, sub-micron CMOS process * 5 V operating voltage for core, ability to run output clocks at 3.3V or 5V for easy interface * Available in commercial and industrial temperature versions VDDIO
Description
The MK2732-06 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The on-chip Voltage Controlled Crystal Oscillator (VCXO) accepts a 0 to 3 V input voltage to cause the output clocks to vary by 100 ppm. Using ICS/MicroClock's patented VCXO and analog Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 10 MHz to 14 MHz pullable crystal input to produce up to three output clocks. ICS manufactures the largest variety of clocks for Set-top boxes and Communications. Consult ICS to eliminate VCXOs, crystals, oscillators and buffers from your board.
Block Diagram
VDD5 2
S1, S0
VIN 10-14 MHz X1 pullable crystal
X2
PLL/Clock Synthesis Circuitry Voltage Controlled Crystal Oscillator
Output Buffer
CLK1
Output Buffer Output Buffer
CLK2
REFCLK
OE (all outputs) 1 Revision 120600 Printed 12/21/00 Integrated Circuit Systems * 525 Race Street * San Jose * CA *95126 *(408) 295-9800tel*www.icst.com
MDS 2732-06 C
PRELIMINARY INFORMATION
MK2732-06 Low Phase Noise VCXO+Multiplier
Clock Select Table
Pin Assignment MK2732-06
X1 VDD5 VDD5 VIN GND GND S1 OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 REFCLK NC GND CLK2 VDDIO S0 CLK1
S1 0 0 0 M M M 1 1 1
S0 0 M 1 0 M 1 0 M 1
Input 13.248 13.248 13.248 13.248 13.5 13.5 13.5 Test mode 13.5
CLK1 52.992 13.248 13.248 52.992 54 54 27 27
CLK2 35.328 35.328 35.328 35.328 27 27 54 27
Refclk off off on on off on on on
16 pin (173 mil) TSSOP Pin Descriptions
Number 1 2, 3 4 5, 6, 13 7 8 9 10 11 12 14 15 16 Name X1 VDD5 VIN GND S1 OE CLK1 S0 VDDIO CLK2 NC REFCLK X2 Type XI P VI P TI I O TI P O O XO
0=connect directly to GND M=leave unconnected (floating) 1=connect directly to VDDIO off=output stopped low.
Description Crystal connection. Connect to a pullable crystal of 10-14.318 MHz. Core VDD. Connect to +5V. Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO. Connect to ground. Select input #1. Selects outputs per table above. Do not exceed VDDIO. Output Enable. Tri-states outputs when low. Do not exceed VDDIO. Clock Output #1 per table above. Amplitude = VDDIO. Select input #0. Selects outputs per table above. Do not exceed VDDIO. Input and output VDD. Connect to +3.3V or +5V. Clock amplitude matches this voltage. Clock Output #2 per table above. Amplitude = VDDIO. Nothing is connected internally to this pin. Buffered crystal VCXO clock Crystal connection. Connect to a pullable crystal of 10-14 MHz.
Key: I = Input; TI = tri-level input; O = output; P = power supply connection; VI = analog voltage input; XI, XO = crystal pins.
External Components
The MK2732-06 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01F should be connected between VDD5 and GND on pins 3 and 5, and VDDIO and GND on pins 11 and 13, as close to the MK2732-06 as possible. A series termination resistor of 33 may be used for each clock output. The input crystal must be connected as close to the chip as possible. The input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load capacitance is recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT consult the application note MAN05 for layout guidelines.
MDS 2732-06 C
2 Revision 120600 Printed 12/21/00 Integrated Circuit Systems * 525 Race Street * San Jose * CA *95126 *(408) 295-9800tel*www.icst.com
PRELIMINARY INFORMATION
MK2732-06 Low Phase Noise VCXO+Multiplier
Minimum Typical Maximum 7 VDD+0.5 70 85 260 150 5.0 3.3 2.5 2.5 5.25 5.25 1.5 0.8 VDD-0.5 0.5 2.4 0.4 VDD-0.4 23 5.8 100 7 0 10 0 3 14 1.5 1.5 60 150 -115 100 Units V V C C C C V V V V V V V V V V V mA mA mA pF ppm V MHz ns ns % ps dBc/Hz ppm
Electrical Specifications
Parameter Supply voltage, VDD Inputs and Clock Outputs Ambient Operating Temperature
Ambient Operating Temperature, MK2732-06GI
Conditions Referenced to GND Referenced to GND Industrial Temperature Max of 10 seconds
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5 0 -40 -65 4.75 3.13 3.5 OE OE S1, S0 S1, S0 IOH=-25mA IOL=25mA IOH=-8mA No Load No Load Each output S1, S0, OE All clocks 2
Soldering Temperature Storage temperature Core Operating Voltage, VDD5 I/O Operating Voltage, VDDIO Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH, binary input Input Low Voltage, VIL, binary input Input High Voltage, VIH, trinary inputs Input Low Voltage, VIL, trinary inputs Output High Voltage, VOH Output Low Voltage, VOL Output High Voltage, VOH, CMOS level Operating Supply Current, IDD Operating Supply Current, IDDIO Short Circuit Current Input Capacitance Frequency synthesis error VIN, VCXO control voltage Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Maximum Absolute Jitter, short term Phase Noise, relative to carrier Output pullability, note 2 Notes:
DC CHARACTERISTICS (VDD5 = 5.0V, VDD3.3 = 3.3V unless noted)
AC CHARACTERISTICS (VDD5 = 5.0V, VDD3.3 = 3.3V unless noted)
0.8 to 2.0V 2.0 to 0.8V At VDDIO/2 10 kHz offset 0V VIN 3V
40
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With an ICS/MicroClock approved pullable crystal.
MDS 2732-06 C
3 Revision 120600 Printed 12/21/00 Integrated Circuit Systems * 525 Race Street * San Jose * CA *95126 *(408) 295-9800tel*www.icst.com
PRELIMINARY INFORMATION
MK2732-06 Low Phase Noise VCXO+Multiplier
16 pin TSSOP
Millimeters Min Max 1.10 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.65 BSC 0.50 0.70 0.05 0.15
Package Outline and Package Dimensions
E
H
D Q e c b
h x 45 A L
Symbol A b c D E H e L Q
Ordering Information
Part/Order Number MK2732-06G MK2732-06GTR MK2732-06GI MK2732-06GITR
Revision history: Version Revision A 031199 B 040699 C 120600 Comments Original Corrected typo on package width from 73 to 173 mil. Added IDDIO, IDD, jitter. Changed 1M selection to Test Mode. Changed aspect ratio of pinout package. Changed features to show xDSL and MPEG. Added Industrial Temperature version of device (MK2732-06GI and MK2732-06GITR)
Marking Shipping packaging ICS (top line) tubes MK27326 (2nd line) tape and reel ICS (top line) tubes MK27326I (2nd line) tape and reel
16 pin TSSOP 16 pin TSSOP 16 pin TSSOP 16 pin TSSOP
Temperature 0 to 70 C 0 to 70 C -40 to -85 C -40 to -85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 2732-06 C
4 Revision 120600 Printed 12/21/00 Integrated Circuit Systems * 525 Race Street * San Jose * CA *95126 *(408) 295-9800tel*www.icst.com

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